Neuromorphic hardware and FPGA synthesis
From a portable spiking model to gates on a chip — and the sub-microsecond triggers it enables.
Neuromorphic hardware runs spiking networks natively, computing only when a spike arrives rather than clocking dense matrix multiplies. Research substrates range from digital many-core chips to large real-time simulators, each with its own event-communication fabric. The common problem is portability: a model built for one substrate should run on another without being rewritten.
A neuromorphic intermediate representation addresses this by describing a spiking network in a substrate-independent form that different back-ends can compile. From there, field-programmable gate arrays provide a route to custom hardware without a fabrication run: the network is synthesised to reconfigurable logic, where fixed-point datapaths and deterministic timing make sub-microsecond responses achievable.
The federation uses both ends of this path. The neuromorphic studio compiles from the portable representation toward FPGA logic, and the merge-and-integration fabric drives sub-50-nanosecond trigger synthesis on FPGA for pulsed-plasma experiments — a place where deterministic hardware timing is not a convenience but a requirement.
The vocabulary of the topic.
- Event-driven computation
- Hardware that acts only when a spike arrives, trading dense throughput for energy.
- Intermediate representation
- A substrate-independent description of a spiking network that multiple back-ends compile.
- FPGA synthesis
- Mapping a network to reconfigurable logic — custom hardware without fabrication.
- Deterministic timing
- Fixed-latency logic that makes sub-microsecond, repeatable triggers possible.
Studios working on this.
Each runs standalone in its own repository and federates its evidence through the platform.
Run it, don't take it on faith.
The runnable lessons and sealed measurements this site ships for the topic.
Read it at source, in order.
Canonical references for the topic, ordered from the foundations to current work. Every one was verified at source — a DOI resolves through doi.org, a standard through its issuer — so each link goes to the real record.
Put to work
- 1
A digital neuromorphic processor with on-chip plasticity.
- 2 Paper A million spiking-neuron integrated circuit with a scalable communication network and interface
TrueNorth — a large-scale digital spiking chip and its event fabric.
- 3 Paper The SpiNNaker Project
A many-core architecture built to simulate spiking networks in real time.
Current work
- 4
NIR — the portable spiking-network representation the studio compiles from towards FPGA.
Related topics.
Where this topic connects to the rest of the federation's work.